Field programmable gate arrays (FPGAs) are well known in the art. An FPGA comprises an array of configurable logic blocks (CLBs) which are programmably interconnected to each other to provide a logic function desired by a user. U.S. Pat. No. 4,870,302, reissued as U.S. Pat. No. Re. 34,363, and incorporated herein by reference, describes a well known FPGA architecture. Other publications, such as U.S. Pat. No. 4,758,745, U.S. Pat. No. 5,243,238, and published application WO 93/05577, also incorporated herein by reference, describe other FPGA architectures. The Xilinx 1993 Data Book entitled "The Programmable Logic Data Book", available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, also incorporated herein by reference, describes several products which implement a number of FPGA architectures.
An FPGA is considered to be a general purpose device, i.e. being capable of performing any one of a plurality of functions, and is programmed by an end user to perform a selected function. Because of this design flexibility, a general purpose FPGA includes a significant number of wiring lines and transistors which remain unused in most applications. Moreover, FPGAs include overhead devices which facilitate programing of the FPGA to do the specified function. These overhead devices undesirably add area to the FPGA chip. To compensate for this overhead, it is commercially important to reduce the cost of the FPGA. One way to reduce the cost is to make the FPGA less general purpose, that is, to eliminate some configuration options which are less commonly used. However, this reduction in configuration options reduces the value of the FPGA to customers, who may not be able to predict which options will be needed. Therefore, a need arises to eliminate area while maximizing configuration options.